In Radio Frequency (RF) or wireless communication networks, transmitters and receivers are employed to communicate data. Looking specifically, however, to RF receivers, these devices generally operate in one of two modes: direct conversion or intermediate frequency. Each of the different modes offers different sets of benefits and drawback, which are taken into consideration when a particular receiver is designed.
Turning first to FIGS. 1A and 1B, a receiver 100 for an intermediate frequency architecture can be seen. With this intermediate frequency architecture, the analog input signal AIN is centered at an intermediate frequency by input circuitry (mixer 104 and oscillator 102, for example) and provided to analog-to-digital converter (ADC) 106. ADC 106 operates as a time-interleaved (TI) ADC with sampling rate of twice the bandwidth of the signal of interest (x(t), for example). Constructing such a TI ADC, such as ADC 106, however, generally requires compensation circuitry to correct for different mismatches that are often present in TI ADCs.
As can be seen in FIG. 1B, ADC 106 includes several mismatch correction circuits. As shown, ADC 106 is a dual channel ADC, meaning that two ADCs 108 and 110 are employed. Each of these ADCs 108 and 110 are clocked by clocking circuitry (buffer 116 and adjustable delay elements 112 and 114, for example). In this configuration, the clock signal provided to ADC 108 is substantially the same as the sample clock signal CLK, while the clock signal provided to ADC 110 is substantially the same as the inverse of the clock signal CLK. Direct Current (DC) offset circuit (adders 128 and 124 and DC offset estimation circuit 118, for example) and gain mismatch circuit (adders 126 and 130 and gain mismatch correction circuit 120, for example) provide gain and DC offset correction. Additionally, timing skew estimation circuit 122 provides adjustments to delay elements 112 and 114 to provide timing skew correction.
Turning now to FIGS. 2A and 2B, a receiver 200 with a direct conversion architecture can be seen. With this architecture, ADC 106 operates at baseband with the signal centered at 0 Hz. In particular, input circuitry (oscillators 202 and 208 and mixers 204 and 206, for example) provides in-phase (I) and quadrature (Q) signals to ADC 210. As with ADC 106, ADC 210 also employs circuitry to correct for different mismatches. Some difference, though, between ADCs 106 and 210 are that each of the ADCs 108 and 110 of ADC 210 use the same clock signal (the sample signal CLK, for example) and that the time skew estimation circuit 122 is replaced with the IQ correction circuitry (IQ mismatch estimation circuit 220, multipliers 222 and 224, and adders 214 and 218, for example) to correct for IQ mismatch.
Some other conventional circuits are: U.S. Pat. No. 7,002,505; U.S. Pat. No. 7,277,040; and U.S. Pat. No. 7,352,316.